Semiconductor Engineering

The Era Of Packetized Scan Test Has Arrived

For decades, process and design scaling has triggered the adoption of transformative test solutions. About twenty years ago, when at-speed test became a de-facto requirement, on-chip compression ...
Electronic Design

The Benefits—And Hazards—Of Scan Compression

IC designers now have a powerful weapon in the struggle against rising test costs: commercially available EDA solutions that provide fast and effective means to implement scan compression on-chip. By ...
Semiconductor Engineering

Analog Scan: Unlocking A New Era In Mixed-Signal Test

Anyone involved in IC product sign-off that includes a mixed signal design portion knows that developing robust tests for these intricate designs has historically been a significant bottleneck, no ...
Electronic Design

Making Test Lean Again

Circuit board test, like any step in the PCB assembly process, benefits from lean manufacturing practices that continually improve process steps. If lean manufacturing principles were applied to ...
EDN

SynTest readies scan-test data compaction tool

SAN MATEO, Calif. — Design-for-test tool vendor SynTest Technologies Inc. is putting the finishing touches on a test-data volume compaction technology for scan-based design. VirtualScan will help ...